A Comparative Study of Directed Testing vs UVM-Based Random Verification

Abstract

In this thesis, both directed testing and constrained random verification using the Universal Verification Methodology (UVM) approach are considered for verifying the functionality of an Advanced Highperformance Bus Lite (AHB Lite) protocol design. With today’s SoCs being very complex in nature, there is a great need to choose a proper verification methodology to ensure that all aspects comply with the protocol. This research provides a solution for this challenge by implementing both approaches on an AHB Lite slave memory design and then analyzing their performance based on certain quantitative metrics.. The directed test methodology validates basic AHB transactions such as single transactions, WRAP4 burst increments, and write then read transactions with manual stimulus with static address and known data patterns. The methodology based on UVM-Universal Verification Methodology uses a complete verification environment with a transaction level sequence item with protocol constrained, agent with driver and monitor, automation reference model scoreboard, and functional coverage collection from covergroups. Constrained random test stimuli generation covers the legitimate transaction space in different seeds, aiming at scenarios not anticipated in directed tests. Both approaches are looked at using a few different factors like functional coverage percentage, code coverage, simulation throughput, test code volume, debugging complexity, and how well the testbench architecture scales. The results show that directed testing gives us a clear and easy way to debug known scenarios with just a bit of infrastructure. On the other hand, UVM-based constrained random verification manages to cover a lot more cases with fewer lines of test code, plus it brings to light some corner case behaviors that might get missed in tests that are written by hand. Overall, these findings are pretty useful for verification engineers when they're picking the right method for AHB-based digital IP verification in today's SoC development projects.