Design And Implementation Of High Speed Low Power Integer Multiplier

Abstract

Wireless communication system became tremendously popular in recent years these system can be implemented using digital signal processors. Most digital signal processing systems incorporates a multiplication unit to implement algorithm such as correlation, convolution, filtering and frequency analysis. These algorithms are used in application such as finite impulse response (FIR), infinite impulse response (IIR), discrete cosine transforms (DCT), and fast Fourier transforms (FFT). There is rapid increase in the popularity of portable and wireless electronic devices, like portable video player, laptop computers and cellular phones which rely on digital signal processors. Thus there is requirement of best performance without power sacrifice. So the need of low power multiplier is inevitable. Since multiplication is one of the most critical operations in many computational systems, there have been many algorithm proposed in the literature to perform multiplication. This thesis focuses on implementation of an efficient algorithm which is applicable to low power application. The implementations developed for this study indicate that traditional Booth encoded multipliers are superior in layout area, power, and delay to non-Booth encoded multipliers. Redundant Booth encoding further reduces power requirements. Finally, only half of the total multiplier delay was found to be due to the summation of the partial products. In the summation network, full adder is most power hungry block. Thus, the realization and power optimization of full adder block has been done in TSMC 0.35ì CMOS technology using mentor ASIC design tool. The final 16 X 16 multiplier operates at 8.550ns (Maximum Frequency: 116.952MHz) with an approximate power dissipation of 1mW.