Different access mechanisms for set-associative cache architecture for reduced power consumption

Abstract

In recent years, power consumption has become one of the most critical design concern. Power dissipation by microprocessors is getting larger, which leads to serious problems in terms of allowable temperature and performance improvement. Cache memory is effective in bridging the growing speed gap between a processor and relatively slow external main memory. Today, almost all the commercial processors, not only high performance microprocessors but embedded ones, have on-chip cache memories. The processor accesses the main memory (DRAM) via the cache memory in order to improve the performance of the system. This dissertation demonstrates that cache utilization is an important performance and power-related metric by focusing on the ordering of cache line accesses. Set-associative cache organization achieves lower miss rates resulting in improved system’s performance but at the same time result in significant power dissipation. Hence, In order to achieve low power consumption, novel set-associative cache architectures have been proposed in which the process of accessing the tag sub-arrays and the data sub-arrays associated with the respective ways of four-way set associative cache architecture takes place in two phases unlike the conventional set-associative cache architectures. This paper also proposes a valid bit pre-checking architectural scheme for conventional parallel set-associative cache architecture in order to achieve low power consumption. The behavioral modeling of the architectures was done using Verilog HDL. The simulation and synthesis results illustrate that the proposed phased parallel-access and phased sequential-access set-associative cache architectures showed significant power reduction of 28% and 35.36% on an average as compared to conventional parallel-access and conventional sequential-access set-associative cache architectures. The conventional parallel set-associative architecture with valid bit pre-check technique also showed an average reduction of 19.88% in power consumption over conventional parallel-access set-associative architecture.