Analysis and Implementation of Various Adders and Multipliers with Power and Performance Perspectives

Abstract

The goal of this thesis is to analyse and compare various adder and multiplication schemes for high-speed and low power operations. Since the various filter designs found in the Digital Signal Processing applications, require computationally efficient Multiply and Accumulate operations so the blocks with the desired characteristics have to be chosen carefully. Various techniques have been proposed to design multipliers which are efficient in terms of performance, low power consumption and area. The multiplier is a fairly large block of a computing system. The amount of circuitry involved is directly proportional to the square of its resolution i.e. a multiplier of size n bits has O (n2) gates. For multiplication algorithms performed in DSP applications latency and throughput are the two major concerns from delay perspective. Latency is the real delay of computing a function, a measure of how long the inputs to a device are stable is the final result available on outputs. Throughput is the measure of how many multiplications can be performed in a given period of time; multiplier is not only a high delay block but also a major source of power dissipation. That’s why if one also aims to minimize power consumption, it is of great interest to reduce the delay by using various delay optimizations. There have been many algorithms proposals in literature to perform accumulationmultiplication, each offering different advantages and having trade-offs in terms of speed, circuit complexity, area and power consumption. In this thesis, a new architecture for a high-speed MAC is designed in which, the computations of multiplication and accumulation are combined and a hybrid-type CSA structure is used to reduce the critical path and improve the output rate. It uses Modified Booth’s Algorithm based on 1’s complement number system. A modified array structure for the sign bits is used to increase the density of the operands. A carry look-ahead adder (CLA) is inserted in the CSA tree to reduce the number of bits in the final adder. It has been found that Booth Wallace multiplier is most efficient among all, giving optimum delay, power and area for multiplication. Low power modified Booth recoder and pipelining techniques have been used to reduce power and delay.