Design and Implementation of A Python-Based Automation Framework For Analog And Mixed-Signal (AMS) Verification

Abstract

The rapid growth in the complexity of mixed-signal integrated circuits has placed enormous demands on the analog and mixed-signal (AMS) verification process. Manual setup of testbenches, AMS Connect Files (AMSCFs), and simulation environments across multiple PVT corners is time-consuming and a significant source of inconsistency and error. This thesis presents the design and implementation of a Python-based automation framework that addresses these challenges in a systematic and integrated manner. The proposed framework automates key steps in the AMS verification flow: netlist parsing for top-module and pin extraction, duplicate module detection, testbench template generation, AMSCF generation across PVT corners, simulation control, and regression management. Built around Real Number Modeling, the tool currently parses SystemVerilog and Verilog-AMS netlists and integrates with the industry-standard simulators Cadence Xcelium and Spectre; extending this support to SPICE-based netlists is identified as a direction for future work. A graphical user interface (GUI) enables engineers to interact with the framework without requiring deep knowledge of the underlying implementation. The framework was validated on the netlist of the design under test, reducing full test environment setup time from one to two working days to a few minutes. A complete set of twenty-seven PVT corner AMSCF files was generated automatically, all verified to be syntactically correct, and the generated testbench template, with a One-Wire protocol instantiated, compiled successfully in Cadence Xcelium without manual correction. An AI agent built on LLM such as Claude Sonnet 4.6 was further integrated to generate protocolaware test sequences from natural language prompts, producing multi-step analog stimulus from a single description, though minor human review remained necessary for timing-critical parameters. These outcomes confirm that the proposed framework substantially reduces manual effort in AMS verification setup while remaining accessible to engineers across varying experience levels.