Low Power Multiplier Design using Gate Diffusion Input CMOS Logic

Abstract

The main objective of this thesis is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. Especially, this work focuses on the reduction of the power dissipation, which is showing an ever-increasing growth with the scaling down of the technologies. Various techniques at the different levels of the design process have been implemented to reduce the power dissipation at the circuit, architectural and system level. Furthermore, the number of gates per chip area is constantly increasing, while the gate switching energy does not decrease at the same rate, so the power dissipation rises and heat removal becomes more difficult and expensive. Then, to limit the power dissipation, alternative solutions at each level of abstraction are proposed. The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers. In this thesis work, a new CMOS logic style called Gate Diffusion Input is discussed (GDI). GDI basic cell is very similar to basic CMOS logic style but it enables us to design complex functions with fewer gates as compared to CMOS, which further reduces the power consumption of the circuit. Multiplier is one of the most commonly used circuits in the digital devices. Multiplication is one of the basic functions used in digital signal processing. Most high performance DSP systems rely on hardware multiplication to achieve high data throughput. There are various types of multipliers available depending upon the application in which they are used. Full Adder is the main block of power dissipation in multiplier. So reducing the power dissipation of full adder ultimately reduces the power dissipation of multiplier. Dynamic component of power is reduced in GDI techniques as source of pMOS is not permanently connected to Vdd. It also reduces the latency of the circuit.