Verification of a DFI-Based DDR4 PHY Bridge for DDR PHY Modules

Abstract

In this paper we introduce a high-performance DDR4 SDRAM DDR PHY Training Unit design, this design is independent of the SOC and will only work with the PHY for its training and will provide a better handshake mechanism between PHY and DDR PHY Training Unit. Our DDR PHY Training Unit is able to perform DRAM initialization, refresh, and calibration. Its design is extensible, allowing for further development of other types of DDR4 memory controllers and adaptation for various DDR4 speed grades. The development process involved creating the DDR PHY Training Unit’s logic blocks in RTL from the ground up. Standalone verification of each designed module was conducted, followed by the coverage plane was created to do the complete validation of the entire integrated product. To evaluate the performance of our DDR PHY Training Unit, we conducted extensive assessments using both EEMBC benchmarks and synthetic benchmarks in simulation. These evaluations provide a comprehensive comparison of their performance across various scenarios, offering valuable insights for further developments in the field.