Design and Implementation of a Low Power High Speed Floating Point Adder

Abstract

The demand for high performance, low power floating point adder has been on the rise during the recent years particularly for Digital Signal Processing applications. This thesis explores a new architecture for a low power, IEEE compatible, floating point adder that is fast and has low latency. The functional partitioning of the adder into three distinct data paths allows activity reduction which leads a fast addition operation. The switching activity function of the designed adder is represented as a three state of Finite State Machine. During any given operation cycle, only one of the data paths is active and simultaneously the logic assertion status of the circuit nodes of the other data path are held at their previous states. This results in a low power operation. Critical path delay and latency are reduced by incorporating rounding and Leading Zero Anticipatory Logic (LZA) as well as data path simplifications. This thesis offers a scheme which gives a maximum power saving of 46.2% because the probability that the data will pass through LZA is quite low(approximately 6%) and the probability of bypass is higher (around 18%).The prefix adder, introduced in TDPFADD further reduce the consumed power ( 23.27 mW) and offers 57.4% power saving over FADD.