SOC Test Data Volume Minimization with Testing Time Constraint

Abstract

Imperfections in the manufacturing process of very large scale integrated (VLSI) circuits give rise to manufacturing defects that result in improper circuit operation and which must be screened by the application of test patterns. Scan-based testing reduces the complexity of sequential automatic test pattern generation (ATPG) to combinational ATPG by providing full controllability/observability to the internal state elements. While providing clear benefits in terms of test preparation and fault coverage through structural test of complex system-on-a-chip (SOC) designs, the huge volume of test data (VTD) will render scan based testing ineffective due to limitations of the automatic test equipment (ATE). Although the ATE memory buffers can be reloaded, this will be achieved at the expense of increased time the SOC spends on the ATE, thus raising the cost of test. To overcome the VTD problem, test data compression is employed. The reduction in test data volume will not only reduce ATE memory requirements, but also lower testing time. The testing time of an SOC depends on the test data volume, the time required to transfer the data to the cores, the rate at which the test data is transferred (measured by the cores test-data bandwidth and ATE channel capacity), and the maximum scan chain length. The total test time can be reduced by either reducing the test data volume or by shortening and reorganizing the scan chains. While test data volume reduction techniques can be applied to both hard and soft cores, scan chains cannot be modified in hard cores. Lower testing time will increase production capacity as well as reduce test cost and time to market for SOCs. Therefore new techniques are needed for decreasing test data volume in order to overcome memory bottlenecks and to reduce testing time. Test-data compression offers a promising solution to the problem of reducing the test data volume for SOCs, especially if the cores are not BIST ready. Different compression techniques have been proposed over the years to reduce the test data volume. In this Thesis the multi code compression scheme based on different run length compression techniques (e.g. Golomb, Frequency-directed run-length (FDR), Alternating run-length (AR) and Extended Frequency-directed run-length (EFDR) ) and Huffman is used . To achieve higher compression ratio, an attempt has been made to combine the best properties of all the above techniques so as to utilize all the properties in a single multi code compression scheme. Decoder design for Multi Code Compression Scheme has also been implemented using (tools) which can work for different encoding schemes.