Low Power and High Speed Multiplier Design Using Switched Output Differential Structure

Abstract

Today the use of a CMOS differential style has reached a wide range of development such that complex Boolean functions are performed with less transistor count and less propagation delay. In the CMOS logic structure, the redundant logic has to implement in the PMOS block that same logic have to implement in the NMOS. PMOS has to be large (3 to 4 times) to gain same speed or resistance of NMOS that increases the area required to implement any logic using CMOS structure. There are high speed techniques that are used to reduce the area of the LOAD block, in which the minimum number of PMOS transistor has been used that decreases the area of the any logic design and increases the speed. Some high speed structures such as DCVS-domino, ECDL and SODS structure have been discussed here, in terms of speed and area. The disadvantage of DCVS-Domino and SODS structure is minimum logical depth that increases the delay. The SODS structure has been modified. In the modified SODS, differential structure has been used to implement the output based on the difference generated by the NMOS tree. The difference generated by the NMOS tree is used as an input for cross coupled inverter pair to generate the rail to rail swing at the output. The modified SODS structure has been used in designing of a multiplier, which gives better result than that of the basic SODS adder. The 2-bit and 4-bit multipliers have been designed and simulated on Cadence Spectre. The simulation results have shown that delay of modified structure has been reduced in comparison of basic SODS structure. The delay for 2-bit multiplier has been reduced from 390 ps to 360 ps and also for 4-bit multiplier reduced from 1.25 ns to 950 ps. In this thesis work, Braun algorithm is used for the design of multiplier architecture. The low power technique, MTCMOS, has been used to reduce power dissipation of the multiplier circuit. The low power technique reduced the power dissipation from 272 nW/MHz to 210 nW/MHz for the sum circuit. The design has been simulated at UMC 180nm Technology with power supply of 1.8V in Cadence Analog Design Environment. Layout has been drawn and LVS has been verified. RCX extraction has also been generated with the help of tool.