Synthesis and Optimization of a 4-bit Magnitude Comparator Circuit Using BDD and Pre-Computation based Strategy for Low Power

Abstract

Symbolic model checking has been successfully applied in verification of various hardware circuits. A core technology underlying this success is the Binary Decision diagram (BDD) representation. Given the importance of BDDs in model checking, as a result the computational aspects of BDDs are well understood and BDD based model checking is to be stable in terms of performance. In BDD based realization of logic circuits, the area and power consumption is determined by the total number of nodes. A proper polarity selection of the sub-functions can not only reduce the number of BDD nodes, but also the switching activity. This study addresses the performance issue of 4-bit magnitude comparator specially for low power by developing a general evaluation methodology, and by BDD computation as well as pre-computation strategy.