Area and Power Efficient Register Allocation Technique for the Implementation of Principal Component Analysis

Abstract

In majority of the cases, every variable in the input HDL behavioural description needs to be held in a register and a register can be shared by multiple variables if they have mutually disjointed lifetime intervals. This approach has been proven effective for various DSP algorithms. Efficient utilisation of registers used in various architectures is very important in all aspects for the improved performance and efficiency. In this report, lifetime analysis technique is used for register minimisation. Today multi-dimensional data analysis required in almost every field such as neuroscience, meteorology, oceanography, gene expression, agricultural studies, climate studies, material sciences, ecological studies, in IC designing, etc., as real time operations are expected to handle data efficiently. Many applications like pattern recognition, signal estimation, fault diagnosis, yield diagnosis, and many more requires dimensionality reduction which is typically done using PCA. This paper presents a novel register allocation technique i.e. semi-static allocation technique as well as the conventional technique i.e. forward-backward register allocation technique; for the implementation of PCA incorporating variable reuse technique. The purpose of this paper is to avoid register switching and hence reduction in dynamic power consumption as well as area during the implementation of PCA. Syntheses of verilog codes written for both the techniques were carried out in RC (cadence) tool. In case of generic synthesis, a substantial decrease of 56.867% in power and 56.66% in case of area was observed; whereas, in case of mapped synthesis, significant reduction of 86.145% in power and 74.79% in area was observed for the proposed technique in contrast to the conventional one.