Design and Implementation of Reed Solomon Encoder/Decoder

dc.contributor.authorSolanky, Raghvendra
dc.contributor.supervisorRandhawa, Harcharan
dc.date.accessioned2009-09-14T09:09:38Z
dc.date.available2009-09-14T09:09:38Z
dc.date.issued2009-09-14T09:09:38Z
dc.descriptionM.Tech.(VLSI)en
dc.description.abstractChannel coding is used for providing reliable information through the transmission channel to the user. It is an important operation for the digital communication system transmitting digital information over a noisy channel. Forward error correction technique depending on the properties of the system or on the application in which the error correcting is to be introduced. Reed solomon codes are an important sub class of nonbinary BCH codes. These are cyclic codes and are very effectively used for the detection and correction of burst errors. Galois field arithmetic is used for encoding and decoding of reed solomon codes. Galois field multipliers are used for encoding the information block. At the decoder, the syndrome of the received codeword is calculated using the generator polynomial to detect errors. Then to correct these errors, an error locator polynomial is calculated. From the error locator polynomial, the location of the error and its magnitude is obtained. Consequently a correct codeword is obtained. Block lengths and symbol sizes can be readily adjusted to accommodate a wide range of message sizes. Reed solomon codes provides a wide range of code values that can be chosen to optimize performance. The results constitute simulation of verilog codes of different modules of the reed solomon codes in Xilinx. The results demonstrate that the reed solomon codes are very efficient for the detection and correction of burst errors.en
dc.format.extent17228030 bytes
dc.format.mimetypeapplication/pdf
dc.identifier.urihttp://hdl.handle.net/10266/958
dc.language.isoenen
dc.subjectFPGAen
dc.subjectCodeen
dc.titleDesign and Implementation of Reed Solomon Encoder/Decoderen
dc.typeThesisen

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