Design and Implementation of Low power High Speed Floating Point Adder and Multiplier

Abstract

A fast and energy-efficient floating point unit is always needed in electronics industry especially in DSP, image processing and as arithmetic unit in microprocessors. Many numerically intensive applications require rapid execution of arithmetic operations. Addition is the most frequent operation followed by multiplication. The demand for high performance, low Power floating point adder cores has been on the rise during the recent years. Since the hardware implementation of floating point addition involves the realization of a multitude of distinct data processing sub-units that endure a series of power consuming transitions during the course of their operations, the power consumption of floating point adders are, in general, quite significant in comparison to that of their integer counterparts. Multiplier is an important element which contributes substantially to the total power consumption of the system. Speed is a key parameter while designing a multiplier for a specific application. The objective is to design a 32 bit single precision floating point adder/subtractor and floating point multiplier operating on the IEEE 754 standard floating point representations. Second objective is to model the behavior of the Floating point adder and multiplier design using VHDL. The design of a low power and high speed adder and multiplier is thus the goal of my thesis work. The projected plan is to instantiate a good design and modify it for low power and high speed. The pipelining of these designs target high throughput computations.