Automated Verification of Digital IP

Abstract

IP reuse in SoC has led to faster time to market. However, to cop up with this pace, new practices need to be followed to verify the functionality of IP derivative. These blocks or IPs must be verified independently before shipping to ensure proper working and conformance to protocols that they are implementing. But, since the application of all IPs will vary from SoC to SoC, the verification environment must consider the important features and functions that are critical for that application. Universal verification methodology is the latest verification methodology being followed. To reduce communication overhead between designer and verification engineer, the setup of verification environment can be automated, thus eliminating human intervention which can introduce some errors and providing designer an easy interface to test the IP initially. For this, bus functional model of a master bus interface need to be created to initiate the transactions on IP. These models drive slave interface of the IP in order to confirm the protocol is being followed Every IP being created is packaged using IP-XACT standard (xml format). Along with xml files, generators are created which extract the information from these xml files and generate the various files like C Hardware Abstraction layer, document of memory map, RTL of memory map, etc. In order to increase the productivity of verification at designer end, IP-XACT can be processed and used to verify the functionality of registers. Using IPXACT xml file, all the data related to registers is extracted and a structured database is created in system verilog language. This data can be used for the verification of registers to indicate functional errors on simulation console screen.