SDR Implementation of Convolutional Encoder and Viterbi Decoder Using QPSK Modulation Technique
| dc.contributor.author | Aggarwal, Abhishek | |
| dc.contributor.supervisor | Khanna, Rajesh | |
| dc.date.accessioned | 2014-08-14T06:31:22Z | |
| dc.date.available | 2014-08-14T06:31:22Z | |
| dc.date.issued | 2014-08-14T06:31:22Z | |
| dc.description | ME, ECED | en |
| dc.description.abstract | In today‘s era, efficient transmission is very important. In case of long distance transmission wired approach is adopted. But in wireless approach, efficient transmission as well as efficient reception is required. Moreover, the channel through which the communication is taking place has to be considered efficiently. The transmitted information will get modulated according to the various modulation techniques. Convolutional encoder is one of the techniques, which is used to correct erroneous bits at the receiver end. This technique is also called as forward error correction technique. At the receiver end to decode the convolutional codes, Viterbi decoding technique is used. The Viterbi decoder Algorithm is widely used for estimating and detecting problems in signal processing and digital communications. This algorithm is used to detect signals in communications channels with memory, and to decode the sequential error control codes which results in the enhancement of the performance of digital communication systems. The applications of the Viterbi decoding algorithm are: digital TV (QAM, ATSC, and DVB-T), satellite communications and radio relay. In this thesis, a complete convolutional encoded communication system in AWGN channel is designed using VHDL code. The complete RTL schematic of convolution encoder, AWGN channel and Viterbi decoder are designed and presented in the thesis. The complete encoded system is tested for QPSK modulation technique and the results are plotted in terms of BER. The complete system can be further implemented in SDR. The timing summary after analysis got is; minimum period is 27.362ns (i.e. maximum frequency is 36.547 MHz). Maximum input arrival time before clock is 4.213ns and maximum output required time after clock is 4.182ns. | en |
| dc.format.extent | 1765059 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/10266/2902 | |
| dc.language.iso | en | en |
| dc.subject | AWGN,SDR, FPGA | en |
| dc.title | SDR Implementation of Convolutional Encoder and Viterbi Decoder Using QPSK Modulation Technique | en |
| dc.type | Thesis | en |
