SOC TEST DATA VOLUME MINIMIZATION WITH LOW POWER CONSTRAINT

Abstract

Test Data Compression is one of the useful techniques for reducing the volume of test data for System-On-Chip (SOC) testing. In this thesis i propose a multi code compression to compress test data of SOC‘s. The multi code compression scheme is based on different compression techniques (e.g. Golomb, Frequency-directed run-length (FDR), Alternating run-length (AR), Extended Frequency-directed run-length (EFDR) and IFDR). To achieve higher compression ratio, i have made an attempt to combine the best properties of all the above techniques so as to utilize all the properties in a single multi code compression scheme. Considering the large amount of power required in testing i have also proposed a Double Hamming Distance Reordering scheme. Analysis of different Don‘t Care filling techniques along with above scheme has been made and then using Difference vector technique along with the various don‘t care filling technique has been made so as to increase compression ratio and reduce power simultaneously has also been discussed. We have also compared test vectors generated from two ATPG engine‘s i.e. TETRAMAX(SYNOPSYS) and MILEF and have concluded that MTFILLDRDIFF technique in most cases is best for saving Peak and Average power by filling up the don‘t care bits in the uncompacted test set for various ISCAS89 circuits. Experimental results show that the proposed Multi Code Compression Scheme along with double reordered scheme and difference vector can achieve about 40-200% increment in Compression Ratio and a 30-50% decrease in average and peak power with most of the ISCAS89 Benchmark circuits compared with a single code compression scheme using original Test data generated for both the ATPG engines namely TETRAMAX and MILEF. Finally an Decoder design for Multi Code Compression Scheme has also been implemented using (tools) which can work for 6 different schemes with an area overhead of 5262.163086um2 involving 37 Flip Flops.