FPGA Implementation of Booth Encoded Multi-Modulus {2n -1, 2n , 2n +1} RNS Multiplier

Abstract

A novel number system, Residue Number System (RNS) deals with a small set of integers making the arithmetic easier to realize. RNS is a non weighted number system without any significant ordering of digits which makes it suitable for fault tolerant applications. The research work aims at designing a fast efficient RNS based Booth encoded multiplier since multiplication, a very important arithmetic operation, is finding a great use these days in various applications (especially DSP, multimedia and image processing). Due to advances in technology and increasing needs for high speed calculations, it has become really necessary and important to design a fast efficient multiplier. With advances in technology, many researchers have tried and are trying to design multipliers which offer either to the following-high speed, low power consumption, regularity of layout and hence less area or even combination of them in multiplier. However area and speed are two conflicting constraints. So improving speed results always in larger areas. A productive method to speed up the multiplication is reduction in the Partial Product (PP) array. Various techniques exist for the reduction of Partial Products. But according to research, Booth’s algorithm is the most efficient and most widely used. Booth‘s multiplication algorithm effectively multiplies the operands for partial product generation. Booth algorithm is a technique used for partial product generation and reduction i.e. it can be used to minimize the number of iterations or the number of partial products generated. It makes the multiplication speedy making the multiplier efficient.