Design of bypassing multiplier

Abstract

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following- high speed, low power consumption, regularity of layout and hence less area or even combination of them in multiplier. Thus making them suitable for various high speed, low power, and compact VLSI implementations. However area and speed are two conflicting constraints. So improving speed results always in larger areas. This project tries to find out the best trade off solution among the both of them. Generally multiplication goes in two basic steps. Partial product generation and accumulation. In this project, implementation of the bypassing technique has helped in reduction of the power and area. The row bypassing is better as compared to conventional multiplier. On the implementation of column bypassing multiplier the extra circuitry needed is eliminated. The row and column bypassing multiplier results in the reduced switching activity.Thus,less power consumption.