High Speed Multiplier

Abstract

Digital multiplication is one of the most basic functions in a wide range of algorithms. The motivation behind the study of multiplier is driven by need of high speed circuits as with the increasing level of device integration and the growth in complexity of microelectronic circuits, reduction in time delay has come to the fore as a primary design goal. This work uses divide and conquer technique for increasing the speed of the booth multiplier. Booth algorithm already increases the speed of the multiplier by using multi bits of the multiplier at a single time, but it is further increased using the above mentioned technique which divide the given task into smaller tasks (subtasks). Using this technique, n bit multiplier can be implemented like implementing n/2 bit multiplier. In this work, 16-bit and 32-bit multiplier are implemented using this technique which reduces time delay quiet significantly.