Design of Comparator for ADCs

Abstract

Comparators are a key component in a data-converters because they represent the link between the analog and digital domains (i.e. analog signal in and digital signal out and vice versa). In the present work a Track and Latch comparator has been designed.

The comparator consists of a differential input stage, two regenerative flip-flops, and output driver. Comparator has two modes of operation: tracking and latching. In the tracking mode, the preamplifier is enabled to amplify the input difference and tracks the input, while the latch is disabled. In the latching mode, the latch is enabled so that the instantaneous output of the preamplifier is repeatedly amplified and logic levels are produced at the output.

The designed Comparator has 6-bit resolution with power consumption of 1.609 mW for the Clock frequency of 100 MHz for 1pF load. The 0.35 µm TSMC 3.3V CMOS process has been choosen as the target technology.