Modelling of Direct Tunnelling Gate Leakage Current through High-k/SiO2 Gate Stacks

Abstract

The scaling down of device dimensions of MOSFETs is accompanied by a decrease in the gate-oxide thickness and an increase in the substrate doping density. When the gate-oxide thickness becomes less than 2 nm, a substantial amount of current flows through the oxide due to Direct tunnelling. High-k dielectrics are being extensively studied to replace silicon dioxide as they allow for higher physical thicknesses of oxides (EOT). In order to maintain a good interface between the gate-oxide and the channel and to prevent mobility degradation, there must be a thin interfacial layer of silicon dioxide between the bulk and high-k dielectric which calls for the introduction of gate stacks. In this work, an analytical model has been developed for gate tunnelling through two layer gate stacks. The results obtained from this model show good agreement with the simulation results obtained using Silvacco (Atlas) tool. The effect of variation of interfacial layer thickness and capping layer thickness on the tunnelling current density has been studied. The study reveals that both these thicknesses must be kept as thin as possible for the gate leakage current density to be minimum. Direct tunnelling through single layer dielectrics has been well studied and analytically modelled for single dielectric layer. The results obtained from this model show good agreement with the experimental results. The impact of variation of gate-oxide thickness and k-value of dielectric on the tunnelling current density has been studied. The tunnelling current density is inversely proportional to the gate-oxide thickness as well as the k-value of the dielectric. The tunnelling current decreases by an order of magnitude of approximately 〖10〗^4 by using gate stacks instead of using only silicon dioxide as dielectric. The polysilicon gate must be replaced by metal gate so as to prevent the formation of interface states between the top gate and high-k layer. An analytical model has been presented for the case of metal gate also.