A High Speed Arithmetic Logic Unit using ROMs

Abstract

There is a flurry of activities going on in designing high speed circuits. Area, speed and power dissipation are crucial parameters for competitive advantage. Fixed point operations like multiplication is an operation essential to signal processing applications such as Fast Fourier Transform (FFT) algorithms, digital filter implementation. Scientific and engineering applications demand exceptionally high floating point performance. For such stringent requirements, design of fast, precise and efficient Arithmetic Logic Unit (ALU) is the goal of every design engineer. In this thesis work, a novel design of ALU is presented. The design makes use of two read only memories (ROMs) for the purpose of addition and multiplication and thereby can be used for other operations like subtraction and division. An indigenous algorithm is developed to implement the design. ModelSim SE 5.5e and Xilinx ISE 6.1i tools are used for simulation and generating synthesis report. The synthesis report of the proposed design compares device utilization and timing summary of the design implanted on Field Programmable Gate Array (FPGA) and Complex Programmable Logic Devices (CPLD).