Pre Silicon RTL Verification of Mixed Signal IPs

Abstract

Validation remains an unavoidable, yet truly difficult and prolonged part of IP configuration and manufacture process. With shortening timelines and expanding time-to-market necessity, IP producing houses are compelled to empty more and more resources into validation. Hence, validation remains an indispensable and essential period of today’s IP design and integration procedure. Validation techniques can be partitioned into two stages: Pre-Silicon Validation and Post-Silicon Validation. For modern ICs with ever increasing RTL complexity, it is becoming very difficult to test all the design specifications using conventional verification techniques having test-benches. There is always a potential for subtle interactions between the various components in a design and because of the design complexity, it is very difficult to confine a realistic set of possible interactions with the help of simulation. Due to this reason, there is an increasing demand for formal property verification. Formal Property Verification consists of exploring all states and transitions in the design by using efficient and domain specific abstraction techniques. These techniques keep into consideration the entire set of possible states in a single operation and hence reduce the human effort as well as the computation time. Pre Silicon verification is not enough to assure complete IP verification. Post silicon support is also required to debug the errors that might have escaped the pre-silicon verification process. Moreover, post silicon verification is done on the manufactured chip, operating at real world frequencies, such that the behavior of the design in the actual environment in which it is intended to be used can be checked.