Design of High Performance Floating Point Multiply and Add Unit

Abstract

Floating point Arithmetic is mainly used in biometrics, medical imaging, applications of audio, motion capture, conferencing, broadcasting etc. Multiplier is considered as the main element of the high performance systems so,it should be designed in such a way that it has high speed, less area and less power consumption. Due to advancement in technology and increasing needs for high speed calculations, the design of such multipliers which offer high speed, low power consumption, regularity of layout and less area was mandatory. However area and speed are two conflicting constraints. So improving speed results always in larger areas. In this thesis a 64-bit high performance Floating Point Multiply and Add (MAC) unit is presented that can perform both fixed and floating point addition and multiplication. An attempt has been made to reduce multiplication time. This thesis explores the possibility of combining fixed and floating point units thereby saving area without sacrificing too much speed. This design has been simulated on Xilinx ISE to analyse delay and power consumption.