Hardware Implementation of Fast Adders for Montgomery Multiplier in Elliptic Curve Cryptography
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Electronics and Communication Engineering Department
Abstract
The Internet of Things network connects the number of devices and gains popularity in the number of applications for transmitting or sharing information. The malicious devices additions to the IoT network disturbs the whole network and steal the user's information. Hence, device authentication is a big concern. To resolve these issues, asymmetric cryptography algorithms are used. In the previous years, the RSA algorithm gained popularity and provide security in large key size which increases the computation time and memory requirement. To overcome these issues, NIST recommended Elliptic Curve Cryptography (ECC) algorithm for data authentication.
In this thesis, the mathematics of ECC algorithm is studied. Based on the studies, it is found that ECC is categorized into the prime and binary field. The prime field is more preferred as compared to the binary field because the requirement to propagate carries is removed and fast inversion algorithms exists. Further, to improve the performance of the ECC algorithm, many multipliers such as Montgomery, Karatsuba, NTT, Comba and their combinations are used. Out of these multipliers, Montgomery is best suitable for fast implementation for ECC due to the fact that it performs both multiplication and modular function simultaneously. Next, to improve the performance of Montgomery multiplier, various parallel prefix adders are studied and among them Kogge-Stone adder is selected because of least delay. The software implementation is done on GCC compiler on LEON-3 processor and hardware implementation is done on Xilinx Vivado for FPGA Basys3 board. The software performance analysis is done on the basis of latency, Cycles per Instructions and hardware performance analysis is done on the basis of slices, maximum frequency, and throughput. In hardware implementation, when comparing ECC with Montgomery multiplier and Kogge-Stone adder with the basic ECC, performance was improved by 15.9 %.
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Master of Technology- VLSI Design
