Design of Low Power Low Noise Operational Amplifier
| dc.contributor.author | Kumar, Anilesh | |
| dc.contributor.supervisor | Agarwal, Alpana | |
| dc.date.accessioned | 2009-09-02T12:50:56Z | |
| dc.date.available | 2009-09-02T12:50:56Z | |
| dc.date.issued | 2009-09-02T12:50:56Z | |
| dc.description | M.Tech. (VLSI Design & CAD) | en |
| dc.description.abstract | In the present work a Low Power Low Noise Operational Amplifier has been designed. PMOS input transistors and weak inversion topology is used for low power and low noise. PMOS transistors as an input stage driver transistor reduce the flicker noise and subthreshold operation reduces the power and noise both. This opamp is designed using TSMC 0.35 technology with a supply voltage of 3.3V. The value of the load capacitance is taken as 5 pF. The power dissipation of the op amp is 31.26 with bandwidth (f3dB) of 1.32 . Total Input Refereed Noise comes out to be 382.68 nV/rtHz at 1 Hz, 123.68 nV/rtHz at 10 Hz and 30.75 nV/rtHz at 1 KHz. | en |
| dc.description.sponsorship | Department of Information Technology (Govt. of India) through SMDP-VLSI Project (Phase – II) and Department of Electronics and Communication Engineering | en |
| dc.format.extent | 3663093 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/10266/931 | |
| dc.language.iso | en | en |
| dc.subject | Low Power | en |
| dc.subject | Low Noise | en |
| dc.subject | Operational Amplifier | en |
| dc.title | Design of Low Power Low Noise Operational Amplifier | en |
| dc.type | Thesis | en |