Low Power Reduced-Tag Architecture for Set- Associative Caches for ARM-Core

Abstract

Most of the embedded processors utilize cache memory in order to minimize the performance gap between memory systems and processor. In embedded systems caches are normally implemented along with processors in one IC. The power consumed by the cache system constitutes the major fraction of the power dissipated by the embedded processors. With increasing computational demands on embedded processors, set-associative caches are being used. In larger caches the major portion of power consumption occurs in address decoding including tag comparisons. Set-associative caches consume larger energy as compared to the direct mapped caches as i) set-associative caches have greater tag bits, ii) they have parallel organization of tag arrays, and hence parallel tag comparison dissipates more energy. It is further analyzed that not all the tag bits are necessary for a cache configuration to achieve a normal performance in terms of hit rate. Hence, architecture with reduced but optimum number of tag bits is possible, which would consume lesser energy. Novel reduced tag architecture for set-associative caches is proposed, which uses lesser number of tag bits in the tag array to minimize power consumption; with minimum hardware modifications. The proposed architecture is inspired from compressed tag architecture for Direct-Mapped caches, proposed by Kwak and Jeon. New modified Way selection methods called MASKED FIFO Way Selection is presented for the proposed architecture that makes the design at par with the conventional set-associative design in terms of performance. An average Tag Reduction of 40% is achieved on different cache configurations. Thereby an energy savings of 10 – 63% for different cache configurations have been achieved. Nonetheless an embedded system architect can chose specific values of optimum tag-length for the specific application programs for specific cache size/associativity.