FPGA Implementation of Pre Encoded Multipliers

Abstract

With the increasing demand of high speed multipliers either embedded or on die new technologies have to be proposed. These new technologies should accomplish the demand of high speed and lesser area. They have to be energy or power efficient and should have low manufacturing cost. Since the introduction of Pre-encoded multipliers many research efforts have been put in using it for various applications but its major scope lies in architecture with high speed. Pre-encoded multipliers for digital signal processing applications based on off-line encoding of coefficients is proposed. To extend this, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values (-1, 0, +1, +2) or (-2,-1, 0, +1) is used leading to a multiplier design with less complex partial products implementation. The partial products used in this pre-encoded multiplier design is designed using primitive NAND gates. The number of gates used is reduced as compared to the previous design as well as the number of stages in Partial Product Generation unit is also reduced .Extensive experimental analysis verifies that the proposed pre-encoded NR4SD multipliers, including the coefficients memory, improve the speed of operation than previous scheme. In proposed system the delay of the architecture design is reduced by replacing the CSA and CLA adder to carry skip adder.