Design and Implementation of First-in First-out Memory

Abstract

A digital signal processor includes a computation block with an arithmetic logic unit, a multiplier, a shifter and a register file. The computation block includes a plurality of registers for storing instructions and operands in a bit format as a continuous bit stream, and utilizes a bit/byte transfer mechanism for transferring in a single cycle a bit field of an arbitrary bit length between the plurality of registers and the shifter. The plurality of registers may be general purpose registers located in the register file or a FIFO. FIFO is also extensively used in iterative computations in digital signal processing like the FFT, on an input data record. A FIFO is also used for storing resampled digital samples for readout at a clock rate which follows the time-averaged horizontal frequency of the received digitized television signal. A color television signal, digitized by a sampling clock asynchronous with respect to the television signal's horizontal synchronizing pulses, is applied to a dynamically programmable digital filter which upsamples or downsamples the received digitized television signal over short time periods in response to time-base disturbances in the signal. The user may also select a higher or lower long-term clock frequency. FIFOs also find use in packet switching techniques. Because of the unscheduled nature of arrivals to a packet switch, two or more packets may arrive on different inputs destined for the same output. The switch architecture may allow one of these packets to pass through to the output, but the others must be queued for later transmission. the most common use of FIFOs is in the interfacing of two clock domains operating at different frequencies.