Low Power Test Pattern Generator for Built In Self Test Circuits

Abstract

The power consumption of the chip during testing is significantly higher than the power consumption of the chip in its target system. This is due to random test pattern generation. This increase in the power consumption of the IC in the test mode is well known in the industry to cause sudden un-repairable device failures resulting in significant manufacturing fall-out directly impacting the cost of the IC. Hence the need of low power testing is very important for better reliability of the devices, to reduce cost and to mainly save power.

The presented work done on a new low power test pattern generator (TPG) can effectively reduce the average power consumption during test application. The inputs at which more switching activity occurs are found and an additional AND/OR gate tree is inserted in between LFSR and CUT at those inputs. This reduces the weighted switching activity (WSA) of the circuit under test (CUT) by suppressing transitions at those heavy inputs and there by reducing the power consumption during testing.