FPGA implementation of binary integer decimal based floating point multiplier

Abstract

Decimal floating point (DFP) arithmetic is important in various applications such as currency conversion, billing, insurance, banking etc, as it is able to produce precise decimal fractions and minimize manual calculations that perform decimal rounding. But binary floating point arithmetic fails to provide correct decimal rounding and exact decimal fractions such as 0.10,0.0418. A multiplier is one of the main component in most digital and high performance systems such as digital signal processors, microprocessors and FIR filters etc. As technology advances, many scientists have tried and are trying to design multipliers which provide either of the following- high speed, low power consumption and hence less area or even combination of them in multiplier. Multiplication is also an important operation in decimal application. This thesis aims to implement Binary Integer Decimal based floating point multiplier using the fastest adder. The maximum time of multiplication is consumed in accumulating the partial products and at the final stage of addition to get the significant product. So, the multiplication time can be reduced if the partial products are accumulated with the help of fast adders and tree multipliers. In this, the binary encoding for DFP numbers also known as BID format has also been implemented, where binary radix of 2 is used. Since BID encoding stores the significant as an unsigned binary integer for effective reuse of existing binary hardware. In this thesis, a hardware design is presented that multiplies BID encoded DFP numbers. An optimized technique that in parallel with significant multiplication is used to detect if rounding is needed and to find the number of product digits that are needs to be rounded. In this, both for significant multiplication and rounding, a single binary hardware along with carry save feedback is used. To design a BID multiplier, the partial products are generated using radix-8 algorithm, then Dadda and Wallace tree structures are used to accumulate partial products and different adders like ripple carry adder, carry select adder or carry look ahead adders are used at final stage to obtain the result. Then multiplier is synthesized and simulated using Xillinx ISE 14.5 targeting Spartan 6 FPGA device. Then their results in the terms of area and delay are compared for BID multiplier using different adders.