Design of Delay-Locked Loop in 0.18-µm CMOS Technology

Abstract

The main objective of this thesis is to align the controlling clock signals for high-speed synchronous interface circuits by decreasing the static phase error. A dynamic de-skew circuit can be used to ensure good clock alignment across variations in process, voltage, and temperature variations (PVT). The Delay-locked Loop (DLL) is such a circuit, using a first-order closed-loop architecture that dynamically aligns its output clock signal with a reference clock signal.

Two basic types of DLL architectures are currently used: analog and digital. The analog DLL uses a continuously variable delay line to remove the skew between the output clock and the reference clock. A digital delay line uses digital elements, making the design more simple and portable, with quantized steps in the delay time.

The Delay-locked Loop is designed and simulated in Cadence Schematic Composer and Spectre respectively using UMC 0.18 μm technology. This thesis presents a DLL design with several new techniques to achieve reduced static phase error, wide lock range, and short locking time at the circuit and architectural level. All the circuit simulations has been done using various schematics of the structures and post-layout simulations are also being done after they all have been laid-out by considering all the basic design rules and by running the LVS program. The lock range is 25-125 MHz, with static phase error of 440 ps.