Study and Design of Comparators for High-Speed ADCs

Abstract

CMOS comparators using preamplifier,suitable for high-speed analog-to-digital converters with High-Speed and Low Offset are presented in this thesis.The topologies using preamplifier completely removes the offset that is present in the input of the latched comparatore.Nearly 18mV offset voltage achieved with the structures making them suitable for flash-type and pipeline data conversion applications.Comparators are designed and simulated in Cadence Virtuoso Analog Design Environment using UMC 180nm technology to validate their performance.Layouts of the comparators have been made in Cadence Virtuoso Layout XL Design Environment.The post layout and process corner simulations with 1.8V supply voltage have been done for the propagation time delay,offset voltage and power dissipation.The minimal propagation time delay of 2 ns,offset voltage of 18mV,resolution of 0.1mV and power dissipation of 175uW is achieved by the double-clock preamplifier based comparator.The input signal frequency is half of the sampling frequency.The single-clock preamplifier based comparator achieves the minimal propagation time delay of 0.685ns,offset voltage of 18mV,resolution of 36mV and power dissipation of 432.27uW.The input frequency is one eighth of the sampling frequency.