VHDL Implementation of REED-SOLOMON Codes

Abstract

Channel coding is used for providing reliable information through the transmission channel to the user .It is an important operation for the digital communication system transmitting digital information over a noisy channel. Channel coding can use either Automatic Repeat request or Forward Error Correction technique depending on the properties of the system or on the application in which the error correcting is to be introduced. Error – control coding techniques are based on the addition of redundancy to the information message according to a prescribed rule thereby providing data a higher bit rate. This redundancy is exploited by decoder at the receiver end to decide which message bit was actually transmitted. The combined goal of the channel encoder and the decoder is to minimize the channel noise. Block codes and convolutional codes are two main methods to introduce error – correcting codes. Reed – Solomon codes are an important sub – class of nonbinary BCH codes. These are cyclic codes and are very effectively used for the detection and correction of burst errors. Galois field arithmetic is used for encoding and decoding of Reed – Solomon codes. Galois field multipliers are used for encoding the information block. At the decoder, the syndrome of the received codeword is calculated using the generator polynomial to detect errors. Then to correct these errors, an error locator polynomial is calculated. From the error locator polynomial, the location of the error and its magnitude is obtained. Consequently a correct codeword is obtained. Block lengths and symbol sizes can be readily adjusted to accommodate a wide range of message sizes. Reed – Solomon codes provides a wide range of code values that can be chosen to optimize performance. VHDL implementation creates a flexible, fast method and high degree of parallelism for implementing the Reed – Solomon codes. The language can be used as an exchange medium between the chip vendors and the CAD tool users. Different chip vendors can provide VHDL description of their components to system designers. CAD tool users can use it to capture the behavior of the design. Also various digital modeling techniques such as finite state machine descriptions, algorithmic descriptions, and Boolean equations are modeled using the language. The results constitute simulation of VHDL codes of different modules of the Reed – Solomon codes in MODELSIM SE 5.5c. The results demonstrate that the Reed – Solomon codes are very efficient for the detection and correction of burst errors.