Design and Analysis of Some Studies on Low Power Hybrid Adder

Abstract

The mitigation of leakage current is of utmost importance in contemporary CMOS circuits, which are very susceptible to power loss, in order to get optimal performance. CMOS devices consume power in two distinct manners, namely statically and dynamically. As the feature sizes of MOS transistors continue to drop, there has been a corresponding reduction in the lengths of CMOS gates. As a result of this technological progress, integrated circuits may now be densely packed into smaller areas, leading to an increase in package density. The issue of power loss has emerged as a significant design constraint in light of the rapid and exponential growth in system

complexity. In addition, the utilization of embedded memories is more prevalent in System-on- Chip (SoC) designs. Consequently, it is vital to possess a satisfactory memory power profile to

accurately anticipate the overall power consumption of the system. Nevertheless, the memory power model used in commercial Electronic Design Automation (EDA) tools lacks sophistication, hence hindering its ability to provide accurate estimations of power usage. As the field of technology progresses towards the nano scale, the research and development of intricate logic circuits necessitate careful consideration of several factors such as leakage current, active power, delay, and space. To further enhance energy conservation, this work proposes the utilization of low loss one-bit full adder cells across many applications. The optimal dimensions of sleep transistors for one-bit Full Adder cells have been established by the application of a distinctive approach for resizing transistors. The use of this technology resulted in a substantial reduction in both power leakage and delay. This study also analyzed and comprehended the nano scale characteristics of a CMOS transistor

in the entire adder circuit to determine its most efficient operation. The source voltage, band-to- band tunneling of transistors, layer thickness, and cutoff voltage were all decreased for optimal

high-speed performance. By employing various techniques, this resulted in a reduction of the loss of both moving and stationary capabilities. In that instance, when the device was in its sleep mode, leakage current was quite little to spare. The 45nm complete 10-transistor adder offered the lowest delay time across all loads, making it suitable for high-speed applications. The 45nm CMOS technology utilized in the design operated at an input voltage of 0.7V and a temperature of 27°C under standard atmospheric conditions. Implemented an optimal method resulted in a significant reduction in both the power consumption and leakage current of an entire adder cell. Especially for usage in Low Power VLSI Circuits, the hybrid full adder was created. A low power hybrid full adder was created with XNOR and Transmission Gate (TG) logic, combining the two logic models—CMOS and TG based full adder. In terms of power, noise, and delay, the 10T hybrid full adder performed better. The hybrid full adder that was designed achieved a power reduction of 55.9% compared to the static CMOS full adder (28T) and 13% compared to the TG-based full adder (20T). The delay was reduced by 62% and 28.1%, respectively, in comparison to the TG-based full adder and the Static CMOS (28T). The simulation is executed on the Cadence Virtuoso with GPDK at 45nm. Moreover, the Ultra-Low Power Techniques (ULPT) of Multi Threshold Complementary Metal Oxide Semiconductors (MTCMOS), Tri-Mode MTCMOS, and Self Controllable Voltage Level (SVL) Techniques were used to investigate the 10T Junction-Less Double Gate Hybrid Full Adder (10T JLDGHFA) cell. The leakage characteristics of an idle circuit decreased with standard circuit fabrication techniques. Simulation results have demonstrated that the leakage power reduced by 24.09% while the leakage current is reduced by 24.11%. Relative to MTCMOS and SVL technologies, Tri Mode MTCMOS offered a 98.55% higher power density and current concentration. It was implemented with a smaller number of transistors and CMOS could be replaced with Fin FET in the future. Furthermore, downscaling the CMOS technology was identical to Moore’s principle, moved with greater functionality, low power, long lifespan, and VLSI circuits that persisted in the need for more integration. When this deterioration expanded to the nano size, many challenges were propagated and had physical changes. We proposed some reliability parameters to an 8T full adder at 45nm CMOS technology. The reliability parameters NBTI and HCI were evaluated at various operating conditions for a 1 year span. The major techniques in reliability were implemented such as Negative Bias Temperature Instability (NBTI) under PMOS and Hot Carrier Injection (HCI) under NMOS degradation and aging were compared and evaluated. The simulated results indicated that the NMOS under HCI degradation and aging was high at low voltage operation at 0.7V and very high at 1.2V operation to NM2. PMOS deterioration and aging were highly influenced by PM1 and PM2 at all observed voltages. This study examined several design architectures and evaluated their individual merits in the context of multiple bit full adder design using the Modified Gate Diffusion Input (m-GDI) approach, based on relevant data analysis. The findings of this study enhanced the design of forthcoming ALU full adder implementations. As a first step towards further investigation, a thorough examination and subsequent optimization of the design's voltage swing was undertaken.. In conclusion, this study provided a comprehensive analysis of the TG, hybrid, static CMOS, and forthcoming m-GDI full adder, enabling a comparative evaluation of their respective performance characteristics. The transient power of the planned hybrid full adder exhibited a much lower average, with an absolute value approximately equal to 16.65μW. The delay in the sum and carry output was denoted as 50.81ps and 51.19ps respectively. Consequently, a determination was made on the optimal design for a complete adder circuit that minimizes both die area and power consumption. The analysis was based on a predetermined set of factors that were consistently maintained throughout the analogy. The interim operational hours and conditions were same across all three locations. The factors included in the analysis were transistor count, Power Delay Product (PDP), Cout delay, SUM delay, and average transient power.