Design for Testability – Pattern Generation and Simulation of Complex Circuits

dc.contributor.authorKaur, Amandeep
dc.contributor.supervisorVyas, Sumit
dc.contributor.supervisorSharma, Manish
dc.date.accessioned2019-08-23T05:27:35Z
dc.date.available2019-08-23T05:27:35Z
dc.date.issued2019-08-22
dc.description.abstractEven though a circuit is designed error-free, manufactured circuits may not function correctly. Since the manufacturing process is not perfect, some defects such as short-circuits, open-circuits, open interconnections, pin shorts, etc., may be introduced. Points out that the cost of detecting a faulty component increases ten times at each step between prepackage component test and system warranty repair. It is important to identify a faulty component as early in the manufacturing process as possible. Therefore, testing has become a very important aspect of any VLSI manufacturing system. Design for testability presents effective and timely testing of VLSI circuits. BIST architecture is used to test the circuits effectively compared to scan based testing. In built-in self test (BIST), on-chip circuitry is added to generate test vectors or analyze output responses or both.en_US
dc.identifier.urihttp://hdl.handle.net/10266/5678
dc.language.isoenen_US
dc.subjectDFTen_US
dc.subjectATPGen_US
dc.subjectScan Insertionen_US
dc.subjectSimulationen_US
dc.subjectPattern Generationen_US
dc.titleDesign for Testability – Pattern Generation and Simulation of Complex Circuitsen_US
dc.typeThesisen_US

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