Implementation of the Low complexity and High throughput LDPC Decoder

Abstract

LDPC codes are appearing in an increasing number of applications. The main advantage of LDPC codes is that they provide a performance which is very close to the capacity for a lot of different channels. The near Shannon limit error correction capability has lead LDPC codes to become the coding technique of choice in many communication systems and storage systems since their introduction. Some of these applications include, among others, magnetic disc recording, deep space communication etc. LDPC is also used for 10Gbase-T Ethernet, which send 10 GB data on twisted pair cable. As these applications continue to evolve, the trend is shifting toward more and more strict requirements on power consumption, decoding throughput and hardware complexity as part of standard design practice, which has prompted for more efficient LDPC decoder implementations. Furthermore, the LDPC decoders are suited for implementations because that makes heavy use of parallelism. The feature of LDPC codes to perform near the Shannon limit of a channel exists only for large block lengths. The large block length results to increase in hardware complexity and decrease in throughput of decoder. The complexity of decoder multiplied as the length of codeword increase. The trade-off between the hardware complexity and the decoding throughput is a critical factor in the implementation of the practical decoder. In this dissertation work, we proposed methods to decrease the hardware complexity and increase in decoding throughput. We have used partially parallel decoder architecture and reduced complexity algorithm to realize the LDPC decoder. Reduced complexity algorithm has greatly reduced the complexity of the decoder especially routing and check node complexity. The highly concurrent design of the decoder results into a maximum symbol throughput of 92.95 Mbps at maximum of 18 decoding iterations. In this work, we have implemented a 9216 bit, rate-1/2, (3,6) LDPC decoder on Xilinx XC3D3400A device from Spartan-3A DSP family and compare the hardware utilization and decoding throughput to the previously proposed (3,6) LDPC decoder. The design is simulated on ISim simulator and synthesized on Xilinx ISE design suite 13.1