Simulation Analysis of Permutation Passibility behavior of Multi-stage Interconnection Networks

Abstract

There are many different ways to organize computational structures to exploit parallelism. Many research efforts around the world are being conducted with the purpose of determining that hardware and software organizations that are best suited for general purpose parallel processing. The communication subsystems linking processors/memory modules and input/output controllers in a parallel processing system is one of its most important architecture features and has a profound impact on system capabilities, performance, size and cost. An interconnection network of the processors provides the desired connectivity and performance at minimum cost is required for communication in parallel processing systems with a large number of components. Multistage interconnection networks play an important role in the parallel computing systems. In multistage interconnection networks the fixed inter stage connections between adjacent stages exist with a number of switches at each stage that are dynamically set to establish the desired connection to route the requests from the inputs to outputs. The distribution of switches as well as their complexity is very important in designing multistage interconnection networks. The important features in the study of multistage interconnection networks are estimation of complexity, fault tolerant, communication efficiency, performance and cost. In this thesis, a survey of various regular and irregular multistage interconnection networks is made. A new algorithm has been developed for finding the permutation passiability behavior of some regular as well as irregular networks. The permutation passibility behavior of existing regular and irregular networks is analyzed and also the simulation of permutation possibility behavior of some regular as well as irregular networks is defined.