Design and Analysis of Arithmetic Units

Abstract

With the advancement in technology, several applications like the mobile computing, social media, scientific research involving complex computations, data transferring etc., are widely used. This requires a large amount of resources for storage and transmission that calls for a number of modern devices and data centers. The modern devices exhibit a trade-off of power and performance. The novel architectures/designs improve one parameter at the cost of other and fail to improve both the parameters simultaneously. Certain applications such as multimedia, data mining, recognition etc. exhibit error tolerance/resiliency due to non-existence of unique output, redundancy in input data and probability computations. In these applications small amount of error is tolerable and outputs are completely acceptable. For these applications, approximate circuits/design can be developed. Significant research has been done to achieve approximate algorithm/architecture and circuits. Various approximate architectures are presented to reduce power dissipation, area and improved delay. Along with the development of approximate architecture for DSP cores (filters), several approximate arithmetic units are presented. Among the arithmetic unit, adder being the prime component of any digital circuit therefore, several approximate adder architectures are presented. Approximate adders are widely used and under experimentation, nowadays. These approximate adders have been classified into the approximate and accuracy-reconfigurable adders. This report covers the design and analysis of the approximate adder designs. In this report, a simplified reverse carry-propagate adder (SRP) where the carry propagates from most significant bit (MSB) to least significant bit (LSB) is proposed. Further different structures have been proposed depending on the propagating carry. The efficacy of the proposed SRP adders has been calculated on comparison with the state-of-the-art reverse carry adder (RCPA). The proposed SRP has been implemented in Verilog and synthesized with the Synopsys design compiler using 65nm library. The results indicate that for eight-bit numbers, at a constant delay of 0.17 n sec, SRP-FA-II is providing an improved power-area-delay product of 46% over RCPFA-III, about 85.6% improvement over RCA and 96.6% improvement over ACA. For 16-bit numbers, SRCP-FA-II is providing an improved power-area-delay product of 53.73% over RCPFA-III, 70.6% improvement over RCA and about 91.7% improvement over ACA. Finally, for comparative analysis of quality metrics, the Lena image (256x256) has been smoothed by Gaussian smoothing filters (GSF) embedded with the proposed SRP and existing 16-bit approximate adders. The simulation results demonstrate that proposed adder outperforms over the existing designs.