Efficient Packet Switching: Designing and Implementation of Router for High-performance and Low Latency

Abstract

The design and implementation of a 1X3 router, a crucial part of contemporary network communication systems, are presented in this conference paper. FIFO (First-In- First-Out) buffers, a synchronizer, a controller, a Finite State Machine (FSM), registers, and packet switching are all crucial components of the router architecture. This paper provides a thorough explanation of the design, operation, and overall function of each component in establishing effective packet routing and enhancing network performance. System on chip (SoC) technology enables the placement of millions of transistors on a single device. The processing performance of traditional SoCs is constrained by their bus-based communication design. Licon industry segments are increasingly embracing the concept of Network on Chip (NoC), which separates computation from communication. The router is the foundation of the network; thus, it must be designed well to improve the system's performance. In the current study, we concentrate on designing a router input-output protocol. For close loop communication, the proposed system features a virtual cut through mechanism. Router 1x3 has three output ports and one input port. Top-level architecture created in the Verilog HDL language with sub-modules including FSM, Synchronizer, FIFO, and Register. Simulation and synthesis is done on Model Sim and Quartus Prime and Code coverage is found on Questa Sim. This paper presents the design and implementation of an efficient router architecture optimized for low-latency and high-performance packet switching. The modular switching fabric, optimized buffering strategy and efficient arbitration logic in the proposed design allow concurrent packet forwarding while minimizing contention and processing delays. Proposed router architecture supports scalable data transfer and reliable operation under heavy traffic conditions. The design is validated and evaluated through simulation and synthesis allowing improvements in packet handling efficiency, reduced latency and efficient utilization of hardware resources. The evaluation proves that the proposed router could be adequately used in modern day efficient communication systems with desire for fast reliable data transfer.