IP Verification and IP Environment Automation

Abstract

The semiconductor market is a market where the demand of the customer is always increasing to have more and more options available at their hands. Thus to fits more and more options in the chips the complexity of the chips is increasing but, the techniques of verification are not growing as fast as the complexity SoC thus leading to bottleneck of design of cycle. The thesis give a brief description of the previously used techniques and their drawbacks and leads to techniques that are being used in the industries nowadays. In the thesis, the verification at IP level is presented in detail along with technique to automate the verification environment at the IP level. In last the results and future scope are enlisted.