Design and Hardware realization of a 16 Bit Vedic Arithmetic Unit

Abstract

ABSTRACT

This work is devoted for the design and FPGA implementation of a 16bit Arithmetic module, which uses Vedic Mathematics algorithms. For arithmetic multiplication various Vedic multiplication techniques like Urdhva Tiryakbhyam, Nikhilam and Anurupye has been thoroughly analysed. Also Karatsuba algorithm for multiplication has been discussed. It has been found that Urdhva Tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers. Using Urdhva Tiryakbhyam, a 16x16 bit Multiplier has been designed and using this Multiplier, a Multiply Accumulate (MAC) unit has been designed. Then, an Arithmetic module has been designed which employs these Vedic multiplier and MAC units for its operation. Logic verification of these modules has been done by using Modelsim 6.5. Further, the whole design of Arithmetic module has been realised on Xilinx Spartan 3E FPGA kit and the output has been displayed on LCD of the kit. The synthesis results show that the computation time for calculating the product of 16x16 bits is 10.148 ns, while for the MAC operation is 11.151 ns. The maximum combinational delay for the Arithmetic module is 15.749 ns.