Optimal Test Solution for Core based System on Chip

Abstract

The advancement in semiconductor technology has enabled the fabrication of integrated circuits (ICs), which may include billions of transistors and can contain all necessary electronic circuitry for a complete system, so-called System-on-Chip (SOC). A System on Chip (SoC) typically integrates a heterogeneous mix of digital logic, embedded memories, user defined logic (UDL) and analog blocks. The manufacturing process may result in defect chips, for instance due to the base material, and therefore testing chips after production is important in order to ensure fault-free chips. The testing time for a chip will affect its final cost. Thus it is important to minimize the testing time for each chip. To reduce test cost, SoCs are being increasingly tested in modular fashion, i.e. their various design modules are tested separately. For core-based SOCs this can be done by testing several cores at the same time, instead of testing the cores sequentially. Now-a-days due to functional and performance requirements, modern SoC designs are not limited to only one level of design and test hierarchy. Hierarchy imposes constraints on the manner in which tests must be applied to “parent” cores and their “child” cores. In this thesis we explore and analyze all the previous work on wrapper design/TAM co-optimization and test scheduling for testing of SoCs taking into consideration multiple constraints like test access time, core testing time, multiple test sets, interconnect testing etc.. It has been found that all the previous work done in wrapper design/TAM co-optimization and test scheduling for testing has treated all the cores in the SoC as if at same level of hierarchy i.e. flat cores. We make use all the analysis done and use the modified wrapper cell design, Multi-level TAM design technique and a efficient test scheduling algorithm based on Integer Linear Programming for handling the testing of SoC with a mix of hierarchical and non-hierarchical cores. A new test architecture is proposed for test access architecture design of megacore based on pareto-optimal points.