FPGA BASED IMPLEMENTATION OF BIT ERROR RATE FOR HIGH SPEED LINKS

Abstract

Today’s serial data communication rates are continue to increase at the fast pace due to the bandwidth hungry applications like image processing, video conferencing and many medical applications. As data rates are increasing, latency room gets still tighter. It in turn results in increased quality requirement on the interface timing and parasitic capacitance interconnect environment. Bit Error Rate is method to evaluate the quality figure of the communication link. ULPI Interface links are used more and more rather than UTMI interface links due to lesser skew and lower pin counts. USB 2.0 is used for this thesis work but the analysis is generic for all the links. This thesis deals with counting the errors occurs during the High speed USB transmission. Bit errors results due to the improper design and implementation of the link or external noisy environment. Bit error rate is one of the parameter required to analyze the performance of the system. The fundamental purpose of BER is to verify procurement specifications what was specified and what was delivered. It verifies that the device meets the performance, design and implementation requirements identified in the procurement specifications without degradation in performance in any environment. In a nut shell, it demonstrates the quality figure of the communication standard USB2.0 and its performance in noisy environment where jitters and skew affect the performance of the system. The purpose of my thesis is to check the quality figure of the ULPI Interface of the PHY using FPGA based platform.