Analysis and Design of a DRAM Cell for Low Leakage

Abstract

In this thesis, the analysis and design of Dynamic Random Access Memory (DRAM) cell for low leakage have been done. For the analysis, trench capacitor DRAM cell has been considered. For the design of trench capacitor DRAM cell, 0.18 μm submicron nMOSFET as access transistor and the conventional trench capacitor as storage device have been considered. Various DRAM cell structures such as three-transistor memory cell, one-transistor one-capacitor memory cell, capacitorless one-transistor floating body cell and two-transistor floating body cell have been explored. Various leakage mechanisms, such as subthreshold leakage, Gate-induced drain leakage, punchthrough and PN junction reverse bias leakage for an access transistor have been focused. Process-level techniques for leakage reduction, such as light doped drain, retrograde well and halo doping, in the trench capacitor DRAM cell have been discussed and employed. Process simulation and device simulation of trench capacitor DRAM cell have been carried out using the ATHENA/ATLAS packages of SILVACO. The trench capacitor DRAM cell structure has been generated using ATHENA and then it is used as input to device simulator ATLAS for its electrical characterization. Leakage reduction from 256 nA to 2.25 nA in DRAM cell has been achieved using the above mentioned process-level techniques.