Multi-Scenario SoC Timing Closure and Eco Generation in XEON Server Chips at Advanced Tech Nodes

Abstract

In today’s modern VLSI chips, as the process nodes continue to shrink, the impact of process variations has increased significantly. This has given rise to research into extending traditional static timing analysis so that it can be performed statistically. Industry standards now work on the much more advanced Parametric On-Chip Variation (POCV) approach leaving behind the traditional on-chip variation (OCV) approaches. The performance of an integrated circuit (IC) largely depends upon its clock frequency and is mostly evaluated considering the worst-case delays. This pessimism has led industry experts to optimize the design further. The main contributor to the delay of the circuit is the interconnect delays. Hence, the number of scenarios required to analyse and fix the design is enormous and increasing, at deep sub-micron levels. Engineering Change Orders (ECOs) at the deep sub-micron level are used to make small, incremental changes without having to go through the entire design process again. ECOs are essential for handling late-stage design modifications and are critical for saving time, reducing costs, and improving the overall efficiency of the design cycle. This work can be briefly divided into three parts (all performed at the full chip level): i. Performing the timing closure (bifurcated as die wise) ii. Implementing Engineering Change Orders (ECOs) to fix the hold violations iii. Performing the quality checks, before final signoff