Design And Analysis of Nanocrystal Flash Memory Cell Based on Single Gate and Double Gate Mosfet Strutures
| dc.contributor.author | Singla, Anurag | |
| dc.contributor.supervisor | Chatterjee, Arun Kumar | |
| dc.date.accessioned | 2014-08-14T10:49:22Z | |
| dc.date.available | 2014-08-14T10:49:22Z | |
| dc.date.issued | 2014-08-14T10:49:22Z | |
| dc.description | ME, ECED | en |
| dc.description.abstract | ABSTRACT Flash memory is the most widely used non-volatile information-storage device today. Flash memories are ubiquitous in their use as portable storage media in cell phones, cameras, music players, and other portable electronic devices. In conventional flash memory charges are stored on the continuous floating gate. If there is any oxide defect in the tunnel oxide, all the charges on the floating gate will leak back to either source/drain or channel through oxide defect. This not only limits the scalability, but also affects the retention characteristics of the flash memory. With scaling many short channel effects like DIBL, GIDL etc. come in to picture. Due to charge sharing effect gate have less control on the channel region. Due to SCE’s the subthreshold leakage current increases exponentially hence stand by power dissipation increases. In order to overcome the problems associated with conventional flash memory new structure has been proposed in which continuous floating gate is replaced with array of discrete charge storage regions i.e. nanocrystals which are electrically isolated from each other. Further to enhance the performance of the nanocrystal flash memory cell, new structure has been proposed which combines the concept of Double gate MOSFET and nanocrystal flash memory. In this work simulation study of single gate nanocrystal flash memory cell and double gate nanocrystal flash memory cell has been studied and simulated using SILVACO (ATLAS) TCAD tool. The programming and erasing characteristics of memory cell has been analysed. Also the impact of write-pulse’s time duration and value of control gate voltage on programming characteristics of the memory cell has been observed. Finally the results of double gate nanocrystal flash memory cell and single gate flash memory cell are compared. In order to facilitate continued scaling of the control dielectric, we explore replacement of the conventional silicon di oxide dielectric with high-k dielectric materials in single gate nanocrystal flash memory cell. In this work Sapphire (Al2O3) is used as the high-k dielectric. Sapphire is sandwiched between two SiO2 layer and this stacked combination is used as control oxide and observed the programming characteristics of single gate nanocrystal flash memory cell. iv It is found that the performance of double gate nanocrystal flash memory cell is much more enhanced in comparison to single gate nanocrystal flash memory cell. | en |
| dc.format.extent | 12581 bytes | |
| dc.format.extent | 4386548 bytes | |
| dc.format.mimetype | application/msword | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/10266/2918 | |
| dc.language.iso | en | en |
| dc.subject | NANOCRYSTAL | en |
| dc.subject | DOUBLE GATE MOSFET | en |
| dc.subject | FLASH MEMORY | en |
| dc.subject | High - k | en |
| dc.subject | Floating Gate MOSFET | en |
| dc.title | Design And Analysis of Nanocrystal Flash Memory Cell Based on Single Gate and Double Gate Mosfet Strutures | en |
| dc.type | Thesis | en |
