Optimizing the Device Performance of Core-Shell based Junction-Less Field Effect Transistor

Abstract

The miniaturization of dimensions of conventional metal oxide semiconductor field effect transistor (MOSFET) for improving the performance and higher transistor density has accompanied with short channel effects (SCE’s). A rectangular core-shell based double gate junctionless transistor (RCS-DGJLT) has been introduced in this work in which an oppositely doped region known as rectangular core is sandwiched between the rectangular shells. For n- type RCS-DGJLT, the rectangular shells are doped with donor impurities and rectangular core is doped with acceptor impurities and vice a versa for p-type RCS-DGJLT. The RCS-DGJLT device is studied and optimized with design parameters such as shell thickness, core thickness, core doping, oxide thickness, channel length, etc. The optimization of RCS-DGJLT design parameters is investigated with the help of performance parameters such as OFF current (IOFF), ON current (ION), ON/OFF current ratio (ION/IOFF), threshold voltage, drain induced barrier lowering (DIBL), subthreshold slope (SS). The performance parameters of RCS-DGJLT are found to be excellent as compared to conventional DGJLT. The different device engineering has also been applied on the proposed RCS-DGJLT and performance parameters are compared with conventional DGJLT. The study includes Gate misalignment of bottom gate, Doping engineering in proposed device, Gate dielectric engineering, and Spacer dielectric engineering. The simulation study shows that RCS-DGJLT has provided a large tolerance limit to gate misalignment without affecting the performance of the device much unlike DGJLT. During the doping engineering, the different doping type and concentration is incorporated in various regions of RCS-DGJLT. It has been observed that either RCS-DGJLT with oppositely doped core architecture or RCS-DGJLT with oppositely doped core along with heavily doped source/drain extension has given outstanding performance parameters. The effect of gate dielectric in RCS-DGJLT is also explored and an interesting correlation is found among core thickness, core doping, and gate dielectric. Moreover, the study of spacer dielectric on RCS-DGJLT is also carried out. The study reveals that if high k spacers are used in RCS-DGJLT, one must follow heavily doped source/drain extension architecture. Our results have manifested that rectangular core is an integral part of the device, thus any engineering on RCS-DGJLT needs the optimization of the core parameters for better device performance. The AC analysis of the proposed device is also examined to exhibit its potency in analog based applications. The common source amplifier is designed using look up table-based Verilog A model and analyzed. The analog performance parameters have been obtained from the proposed device and found to be comparable with existing results in the literature. It has been observed that the proposed RCS-DGJLT device offers good response to analog-based applications as well. Also, voltage transfer characteristics (VTC) of Complementary metal oxide semiconductor (CMOS) inverter as a digital application using RCS-DGJLT is also presented to see the effectiveness of the device. Moreover, an attempt to develop the analytical model for channel potential of RCS-DGJLMOS is carried out. The central channel potential is validated by varying the thickness of core, total silicon thickness, core doping in RCS-DGJLMOS. The analytical model results are in pretty good agreement with the simulation results obtained using Cogenda Visual TCAD software.