Test Time Optimization of Core Based SOCs Using Heuristic Algorithms

Abstract

The cost of testing SOCs (System On Chip) is related to its test application time. With increase in the complexity, the number of on chip test time increases which further increases the possibility of manufacturing imperfections at deep sub micron level. This increase in the complexity increases number of fault sites which need a high test data volume for testing. This application of high test data volume leads to an increase in test application times. SOC consists of digital, analog and various mixed signal components. The urgent time to market requirement poses many challenges for the design and test engineers. Testing cost has made IC testing more difficult. ITRS semiconductor road map represents that there will be a need of hundred of processors for the future generation of SOC designs which will further increase the test cost. Many techniques have been proposed to reduce the cost by test scheduling, reducing test data volume and optimizing test design mechanisms. In order to reduce the test time, cores needed to be tested simultaneously due to which power consumption increases. The main aim is to schedule all the given cores in the allotted TAM width in most optimum manner. Thus, various combinations have been tried to get optimum results by using the partition based technique which will be explained in detail in the subsequent sections. Test scheduling is proved to be an NP-hard problem. In this thesis report, an algorithm is proposed for scheduling different cores so as to reduce the test time while taking power and bandwidth constraints into consideration. This problem can be reduced into a rectangle packing problem. Experimental results for ITC'02 benchmark circuits show the optimal results achieved. The proposed schemes are applied on three benchmark circuits from Duke University and Philips.